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Doing More with Less: Hardware Security Primitives reusing Existing Circuits for Secure System on Chips | Sachin Taneja | Hardwear.io Webinar
Talk Title:
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Doing More with Less: Hardware Security Primitives reusing Existing Circuits for Secure System on Chips

Abstract:
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Security has become a fundamental constraint in chip design for ubiquitous integrated systems and high-performance computing systems due to the recent emerging attacks. True random number generators (TRNG) and physically unclonable function (PUF) are hardware security primitives responsible for dynamic and static entropy required to establish the hardware-level root of trust for secure system on chip (SoC).

This webinar will describe the basics, prior art and state-of-the-art design for these security primitives. Two novel architectures are then discussed reusing existing circuits for these hardware security primitives on any SoC. The first architecture discusses the TRNG reusing the existing cryptographic hardware, while the second architecture reuses the existing omnipresent embedded memories (SRAM) for unified TRNG and PUF.

Silicon demonstrators with measurement results confirm the efficacy of the unification approach reusing the existing circuits with minimal design changes for low-power and secure SoCs.

Speaker Bio:
Sachin Taneja is currently pursuing the Ph.D. degree in electrical and computer engineering from the National University of Singapore, Singapore. He was with Synopsys Inc., India, as an R&D Engineer from 2013 to 2016 where he was involved in designing high-speed circuits and architectures for on-chip embedded memories. His current research interests include hardware security primitives and in-memory compute accelerators. He was a recipient of the IEEE Solid-State Circuits Society Predoctoral Achievement Award in 2020-2021.
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